Events

Electronic Design & Solutios Fair
Pacifico Yokohama
Japan
January 22 - 23, 2009

Executive Panel
Concurrent Design for LSI and PCB
January 22,  13:00-14:30 - Session 1

DesignCon
Santa Clara, CA
Booth #514
February 2 - 5, 2009

Technical Panel
Multi-Die Chip/Package Co-Design for SiP Applications
Tuesday, February 3 | 3:45 pm - 5:00 pm, Ballroom G

Business Forum Panel
Collaboration across the Changing Design Chain
Tuesday, February 3 | 2:00 pm – 3:30 pm, Room 203/204

Technical Paper
Worst Case Switching Pattern for Core Noise Analysis
Tuesday, February 3 | 10:15 am – 10:55 am, Ballroom J

FREE Exhibits Pass 
($100 value) and a 30% discount off of the paid conference programming

Webinar
At Your Desk
Archive

Chip-Package Co-Design: Applying Chip Power Model in System Power Integrity Analysis