Press Release

TSMC and Apache Address Dynamic Power Closure for Nanometer Design

TSMC’s 5.0 Reference Flow implements Apache’s RedHawk-SDL for verification of dynamic and static power integrity and global I/O SSO

MOUNTAIN VIEW, Calif. - June 7, 2004 – Apache Design Solutions, the technology leader in physical power integrity solutions for system-on-chip (SoC) design, today announced that TSMC has adopted RedHawk-SDL as an integral part of its new Reference Flow 5.0, the industry’s first reference flow to achieve power closure.

Today’s industry-leading semiconductor devices contain tens millions of transistors. Hundreds of thousands of these switches may be toggling at any given time, creating highly dynamic power demands that may result in a power integrity issue. RedHawk-SDL provides full-chip dynamic voltage drop analysis and global I/O SSO (Simultaneous-Switching Output) verification, to ensure that all this activity does not compromise the design.

“As process technology moves to 90nm and below, power integrity due to dynamic supply noise has become a key factor in chips meeting frequency, voltage, and yield requirements,” said Edward Wan, senior director of design services marketing for TSMC. “By adding Apache’s RedHawk-SDL to Reference Flow 5.0, we are able to offer power closure for next-generation SoC designs.”

TSMC Reference Flow 5.0 addresses power closure using RedHawk-SDL’s full-chip Vectorless Dynamic™ power verification suite with cell-based capacity and SPICE-level accuracy. It incorporates the effects of simultaneous switching (core, memory, and I/O), intrinsic and intentional decoupling capacitance, and on-chip and package inductive effects, all of which are neglected by existing static-only analysis solutions. Unlike recently announced pseudo-dynamic approaches that perform sequential static analysis on several sub-windows within a simulation, RedHawk-SDL performs full-chip, true transient, time-point by time-point simulation with built-in SPICE accurate cell characterization of every instance. RedHawk’s cell-based static EM/IR-drop capabilities, which provide a static, snap-shot analysis of IR drop, are also supported in Reference Flow 5.0.

As the number of I/O busses and package pins increase, the effects of global I/O SSO is becoming a major source of supply-noise induced chip failure. Apache’s global I/O SSO flow is based on RedHawk-SDL’s P/G network extraction and NSPICE-PI’s large scale mixed-domain SPICE simulation capabilities. TSMC’s 5.0 Reference Flow includes Global I/O SSO methodology based on Apache’s RedHawk-SDL and NSPICE-PI to address this increasingly important physical power integrity issue, also including package coupling.

“TSMC’s advanced process technologies have been driving the most advanced flow requirements and our mutual customers will benefit from the ongoing collaboration to address the critical challenges of power closure,” said Andrew Yang, CEO for Apache. “We are finding more and more customers facing chip failures due to dynamic power and global I/O SSO issues. RedHawk-SDL was built to address the power integrity problems associated by dynamic supply noise and we are excited to be part of TSMC’s 5.0 Reference Flow and to enable our customers to increase their silicon yield.”

Availability

The TSMC 5.0 Reference Flow is available immediately. The TSMC 5.0 Reference Flow provides a complete solution for power closure and includes Apache’s RedHawk-SDL and NSPICE-PI for dynamic/static power and global I/O SSO verification.

About RedHawk-SDL

Apache’s flagship RedHawk-SDL is a full-chip Vectorless Dynamic™ physical power integrity solution that fills the critical missing link for physical power flows in 130nm, 90nm, and 65nm SoC designs. Certified by TSMC’s 5.0 Reference Flow and correlated with silicon measurements and SPICE, RedHawk-SDL delivers the most accurate power integrity solution on the market. It addresses dynamic power issues such as simultaneous switching outputs (SSO) for core, memory, clock, and I/O, as well as the effects of on-chip inductance, package RLC , and decoupling capacitance.

RedHawk-SDL delivers cell-based capacity with transistor-level accuracy and is the cornerstone of Apache’s physical power integrity flow. It can be used early in the design flow when physical implementation decisions are being made, and throughout the entire design process. RedHawk-SDL enables designers to examine the timing impact of dynamic voltage drop on high performance SoCs, including those utilizing advanced low-power design techniques such as leakage current control, power gating, multiple voltage domains, and multiple threshold transistors.

About Apache Design Solutions

Apache is an EDA software supplier of innovative next-generation silicon integrity platforms for low-power, high-performance system-on-a-chip (SoC) designs. By considering all sources of noise that impacts the design, such as power, signal, package / system IO, substrate, and temperature, Apache’s silicon signoff platform enables designers of leading networking, wireless, communication, consumer, and semiconductor companies to detect, fix, and prevent design weaknesses that can result in reduced yield or failed silicon. Apache’s vendor neutral platform enables designers to adopt any industry’s standard physical design flow and is certified by TSMC’s 5.0 and 6.0 Reference Flow (NYSE: TSM). Apache has direct sales and support offices worldwide with over 40 customers, including 7 of the top 10 semiconductor companies.

Apache Design Solutions, NSPICE, RedHawk, PsiWinder, and Vectorless Dynamic are trademarks of Apache Design Solutions, Inc.

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