Press Release

Apache Introduces PsiWinder, A Combined Power and Signal Integrity Timing Sign-off Solution

Mountain View, Calif. - June 6, 2005 - Apache Design Solutions, the technology leader in physical power integrity solutions for system-on-chip (SoC) designs, today announced PsiWinder, a critical path and clock tree analysis tool that considers crosstalk and dynamic power integrity effects on a chips’ timing. For designs at 90nm and 65nm processes, the quality of SoC timing is greatly affected by dynamic noise. Through a seamless integration with Apache’s silicon-proven RedHawk power integrity solution and the Nspice high performance Spice engine, PsiWinder delivers an accurate transistor-level view within an easy-to-use cell-based environment.

“The consideration of combined power and signal integrity effects requires a transient simulation of instance-based dynamic Vdd/Vss waveforms along with crosstalk noise. Trying to combine these effects in a static timing analysis environment cannot provide sufficient accuracy for signoff. What’s required is a time-point-by-time-point Spice-based simulation solution,” stated Andrew Yang, CEO of Apache. “Apache’s industry leadership position in dynamic power integrity enables us to meet the market’s need by delivering the Spice-accurate timing sign-off solution for designs at 90nm and below.”

PsiWinder delivers the following unique capabilities for critical path timing and clock network analysis, including skew and jitter:

Considers signal integrity (crosstalk noise) effects, including aggressor/victim identification, sensitization, and window alignment.

Includes power integrity (dynamic voltage drop and ground bounce) effects using RedHawk generated instance-specific Vdd/Vss waveforms.

Supports process corner conditions for each device, alignment and transition of each coupling signal, and the minimum and maximum dynamic voltage drop of each cell for a thorough verification of on-chip variation (OCV).

Provides automated Spice netlisting of SoC critical path and clock networks, including all the parasitics for the nets in the path, coupling capacitance, and coupled aggressor gates.

Increases productivity through an integrated high-performance NSpice with embedded distributed processing capability for overnight turnaround on thousands of paths.

Uses SPICE engine, the golden standard for circuit verification, with advanced nanometer device models. Eliminates pessimism built into standard libraries through a precise calculation of actual signal slope and loading.

With PsiWinder, designers are able to quickly and accurately verify the critical path timing and clock tree network for the ultimate timing sign-off of their nanometer designs.

Apache will be demonstrating PsiWinder, along with their complete dynamic power integrity solution, at the upcoming Design Automation Conference (DAC) in Anaheim, California, June 13-17, in booth #409.

Availability

PsiWinder will be available in Q3 of this year. Each PsiWinder license includes 10 integrated Nspice engines for distributed simulation of multiple critical paths with LSF and Sun Grid support. It is licensed on Linux, Sun Solaris, and HP-UX.

About RedHawk

RedHawk is a full-chip Vectorless Dynamic™ physical power integrity solution for SoC power closure sign-off of 130nm, 90nm, and 65nm designs. Certified by TSMC’s 5.0 Reference Flow and correlated with silicon measurements and SPICE, RedHawk addresses dynamic power issues such as simultaneous switching output (SSO) for core, memory, clock, and I/O, as well as the effects of on-chip inductance, package RLC, and decoupling capacitance.

RedHawk enables designers to identify dynamic “hot spots,” examine the impact on timing, and automatically repair the source of supply noise. With RedHawk’s integrated transistor-level characterization and unsurpassed capacity, designers can effectively reach power closure sign-off for high performance SoCs, including those utilizing advanced low-power design techniques such as leakage control, power gating, multiple voltage domains, and multiple threshold transistors.

About Nspice

Nspice is a high capacity, mixed-domain, next-generation Spice for I/O, signal, and power integrity. For high-speed I/Os and interfaces to multi-port/multi-gigabit systems, Nspice directly takes in S-parameter data for 100+ ports and accurately simulates a combination of IC-package-board-connector-backplane topologies. Nspice is fully Hspice compatible with unprecedented performance and capacity, while delivering true-spice accuracy.

About Apache Design Solutions

Apache is an EDA software supplier of innovative next-generation silicon integrity platforms for low-power, high-performance system-on-a-chip (SoC) designs. By considering all sources of noise that impacts the design, such as power, signal, package / system IO, substrate, and temperature, Apache’s silicon signoff platform enables designers of leading networking, wireless, communication, consumer, and semiconductor companies to detect, fix, and prevent design weaknesses that can result in reduced yield or failed silicon. Apache’s vendor neutral platform enables designers to adopt any industry’s standard physical design flow and is certified by TSMC’s 5.0 and 6.0 Reference Flow (NYSE: TSM). Apache has direct sales and support offices worldwide with over 40 customers, including 7 of the top 10 semiconductor companies.

Apache Design Solutions, NSPICE, RedHawk, PsiWinder, and Vectorless Dynamic are trademarks of Apache Design Solutions, Inc.

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