Press Release

Apache’s Complete Dynamic Power Integrity and Timing Sign-off Solutions Demonstrated at 42 nd DAC, Booth #409

Mountain View, Calif. – June 9, 2005 - Apache Design Solutions will showcase a complete suite of physical power integrity solutions for SoC dynamic power, advanced low power design, package/IC co-design, and Spice-accurate timing sign-off at the 42 nd Design Automation Conference (DAC), June 13 – 17 in Anaheim, California. Highlights of the conference include a video showcasing a number of Apache’s customers, presentation and demonstration of Apache’s latest products and technologies, and participation in several panel discussions.

Demonstration of Products and Technologies: Booth #409

RedHawk-EV, the industry’s only silicon proven full-chip vectorless dynamic power integrity solution including hierarchical spatial and temporal memory / IP modeling and automatic noise repair and optimization capabilities.

PowerGate technology, included in TSMC Reference Flow 6.0 for accurate analysis of MTCMOS power-gating off-state leakage current and impact of power-up/power-down on timing (see related press release dated June 9, 2005 "Apache Supports TSMC Reference Flow 6.0 with Dynamic Power Integrity for Advanced Low Power Designs")

Nspice-PI, a high performance, high capacity Spice simulator for large-scale system I/O simulations, such as DDR interfaces.

PsiWinder (NEW), the industry’s first automated Spice timing sign-off solution for clock networks and critical paths with concurrent power and signal integrity effects (see related press release dated June 6, 2005 “Apache Introduces PsiWinder, a Complete Power and Signal Integrity Timing Sign-off Solution”).

Apache Panel Participation:

“EDA Serial Aquirees: You Can Run, but You Can’t Hide” by Keith Mueller, VP of worldwide sales and marketing on Monday, June 13 at 3:00 p.m., DAC pavilion – booth #2269

“Should Our Power Approach be Current?” by Andrew Yang, CEO on Thursday, June 16 at 8:30 a.m., room 210CD

About Apache Design Solutions

Apache is an EDA software supplier of innovative next-generation silicon integrity platforms for low-power, high-performance system-on-a-chip (SoC) designs. By considering all sources of noise that impacts the design, such as power, signal, package / system IO, substrate, and temperature, Apache’s silicon signoff platform enables designers of leading networking, wireless, communication, consumer, and semiconductor companies to detect, fix, and prevent design weaknesses that can result in reduced yield or failed silicon. Apache’s vendor neutral platform enables designers to adopt any industry’s standard physical design flow and is certified by TSMC’s 5.0 and 6.0 Reference Flow (NYSE: TSM). Apache has direct sales and support offices worldwide with over 40 customers, including 7 of the top 10 semiconductor companies.

Apache Design Solutions, NSPICE, RedHawk, PsiWinder, and Vectorless Dynamic are trademarks of Apache Design Solutions, Inc.

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