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DAC 2009 - Booth #722
Visit Apache at booth #722 and learn how to reduce cost and mitigate risk with the industry’s leading power and noise solutions for Chip-Package-System convergence. Attend presentations by leading semiconductor companies and learn about their methdology and experiences with Apache's tools. Sign-up for one of the product and technology roadmap presentations on RedHawk, Totem, Sentinel, and advanced technologies such as IO-SSO, ESD, and SiP/3DIC. Get a first hand experience in running RedHawk and Totem at hands-on-tutorial sessions. DAC User Track presentations give uniqiue opportunity to discover how Apache's tools are being used by leading edge designs. Exhibitor Forum presentations provide technical overview of Apache's latest product offerings. Apache At-A-Glance | | 10:00 | 11:00 | 12:00 | 13:00 | 14:00 | 15:00 | 16:00 | 17:00 | | July 27 | Product Overview | | Advanced Technology | Rambus | | Sentinel | RedHawk | Totem | | | Totem | Sentinel | RedHawk | Product Overview | Totem Tutorial | Totem Tutorial | Advanced Technology | | July 28 | Advanced Technology | TSMC | | Broadcom | Product Overview | Totem | Sentinel | RedHawk | | Product Overview | RedHawk | Totem | Sentinel | Advanced Technology | RedHawk Tutorial | RedHawk Tutorial | | | July 29 | | | Advanced Technology | | | RedHawk | Totem | Sentinel | | Product Overview | Sentinel | RedHawk | Totem | Product Overview | Advanced Technology | | | | July 30 | Totem | RedHawk | Sentinel | | | | | | Customer Presentations - Broadcom: Prototyping to sign-off of 45nm Broadcom Mobility chip design
Harpreet Anand, Principal Engineer Learn how Broadcom achieved early signoff of power/ground noise and reliability by prototyping and analyzing various low power design techniques and optimizing power gate / power pad placements and grid geometry ... (more) - Rambus: High-speed I/O interface supply noise, and reliability analysis
Dr. Ralf Schmitt, Senior Engineering Manager, Signal and Power Integrity Listen to Rambus’ power integrity analysis strategy and how it allowed them to accurately analyze the quality of power supply for large mixed-signal interface system operating at very high-speed I/O data rates ... (more) - TSMC: SiP opportunities and design challenges
Louis Liu, Deputy Director Listen to TSMC's strategy for addressing the challenges associated with SiP designs ... (more) Seats are limited so register today! TO REGISTER Product and Technology Roadmaps - Apache Product Overview: From Prototyping to Sign-off
Learn about Apache’s Chip-Package-System (CPS) convergence platforms including RedHawk - SoC dynamic power integrity, Totem - analog, mixed-signal, and memory power and noise analysis, and Sentinel - IC/Package co-design and SiP solution. TO REGISTER - RedHawk-NX: Next Generation 45nm SoC Power Sign-off
RedHawk-NX is Apache’s next generation full-chip power integrity solution with industry’s first Mesh Pattern Recognition (MPR) technology for handling ultra-large 45/32nm designs. This presentation will discuss the application of RedHawk-NX technology from early-stage prototyping to sign-off, as well as RedHawk Explorer for automatic design weakness and power noise root cause identification. In addition, this session will cover Apache’s advanced low power solution including MTCMOS ramp-up, shut-down, switch RAM, on-chip voltage regulators, and active back-biasing. TO REGISTER - Totem: Analog / Mixed-signal Power and Substrate Noise Coupling
Totem is Apache’s newest power, noise, and reliability solution for analog, mixed-signal, and memory designs. It is a layout-driven solution delivering 100M+ device capacity for concurrent simulation of power/ground, substrate, and package/PCB networks. This presentation will discuss the use of Totem for transistor-level dynamic power, substrate, and EM analysis, as well as its IP model generation capabilities for mixed transistor and cell-based design analysis. TO REGISTER - Sentinel: Chip-Package-System Power, Signal, EMI, and Thermal Analysis
Sentinel is Apache’s chip-package-system platform for power, signal, and thermal integrity, SSO analysis, and EMI validation. Sentinel platform includes PSI (power/signal integrity) for full package/board extraction and analysis with FFEM 3D full-wave technology; SSO for high capacity IO/DDR noise and timing analysis; TI (thermal integrity) for chip-package and SiP thermal co-analysis; and EMI for chip emission modeling and system EMI/EMC radiation analysis. This presentation will discuss unique technologies of Sentinel product line and how they provide a comprehensive solution for chip-package-system convergence. TO REGISTER - Advanced Technologies: I/O-SSO, ESD, and SiP/3DIC
These sessions will cover advanced topics such as noise analysis and its impact on high-speed IOs such as DDR3, clock, and package designs; analysis of electrostatic discharge behavior and the effectivenss of the circuit protection mechanisms; power and thermal challenges associated with SiP and 3DIC/TSV designs. Please contact Apache sales respresentive to reserve your seat. Hands-On Tutorial - Using RedHawk with Explorer to Prototype, Analyze, and Diagnose Root Cause of Advanced Low Power Designs
In this tutorial, you will get a first-hand experience in running RedHawk with Explorer to analyze the power integrity of an advanced low power design, identify location of design weaknesses, and automatically trace back the root cause of the problem. TO REGISTER - Using Totem for Layout-based Analysis of Power, Signal, and Substrate Noise of Analog, Mixed-signal, and Memory Designs
In this tutorial, you’ll get hands-on experience in analyzing dynamic power, signal electro-migration, and substrate noise impact on a full-custom memory design. It will also cover debugging and diagnosing capabilities to help identify the cause of design issues. TO REGISTER Apache at DAC 2009 | DAC User Track Presentations | | ST | Electromagnetic Interference Reduction on an Automotive Microcontroller | Tuesday July 28 | 10:30 AM | Room 132 | | STARC | Power Supply and Substrate Noise Analysis; Reference Tool Experience with Silicon Validation | Thursday July 30 | 9:00 AM | Room 132 | | Cisco | Chip-Package-PCB Co-design: Applying Chip Power Model in System Power Integrity | Thursday July 30 | 2:00 PM | Room 132 | | | | | | | | Exhibitor Forum Presentations | | | De-risking Your Design from Power Noise Impact | Monday July 27 | 2:00 PM | Booth #4359 | | | Power and Substrate Noise Analysis and Design Optimization for High-performance Analog and Custom Design | Wednesday July 29 | 1:00 PM | Booth #4359 | To register for one or more sessions, please select REGISTER of one of the sessions you would like to attend and follow the instructions.
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