RedHawk-MMX

RedHawk-MMX is a power integrity analyses solution for full-custom macros such as embedded memories and analog IPs. It performs power/ground grid check, static IR-drop, dynamic voltage drop, and electro-migration analyses with transistor-level accuracy for design applications such as high-performance I/Os and embedded memory macros. Custom macros validated with RedHawk-MMX can be combined with the cell-based digital content of SoC for full-chip, mixed-mode power analysis.

Benefits

Accurate transistor-level noise modeling
Full-chip capacity with over 1 billion transistors
High-performance power network extraction
Early design stage power/ground weakness checking
"What-if" analysis for power/ground and decap optimization
Layout-based GUI for ease of debugging and diagnosis
Direct GDSII, CDL, and DSPF support for extraction and simulation
Consideration of package parasitics impact
Generates validated macro model for SoC power analysis

Transistor-level Characterization and Modeling

RedHawk-MMX delivers transistor-level accuracy through SPICE-based characterization of each device. The characterization engine extracts effective intrinsic and intentional capacitance, equivalent resistance, and time-variant and voltage-dependent current models. This detailed characterization approach provides both spatially and temporally accurate device models for power integrity analysis.

RedHawk-MMX directly accepts GDSII, CDL (or other SPICE format), and DSPF formatted inputs and generates a physical model of the power/ground structures. It combines the electrical and physical models of the full-custom macro, along with the cell-based digital blocks for full-chip SoC simulation.

Power/Ground Grid Integrity Check

RedHawk-MMX performs P/G grid checks to help designers identify weaknesses in their designs. It provides a report with the ranking of effective power grid resistance of all the transistor pins, in order of severity. By selecting a pin on the list, designers can view the associated pin in the layout to identify and debug the cause of design issues. The designer can also use RedHawk’s FAO (Fix & Optimize) option to repair the weak grid areas and missing vias.

Static IR-drop and EM Analysis

RedHawk-MMX provides a report with the ranking of locations of worst average voltage drop for wires and vias, and average pin voltages for transistors. In addition, a full-chip display of the voltage drop, resistance, and current maps can be used to help identify the cause of voltage drop “hot spots”.

RedHawk’s signal EM (SEM) option helps designers identify location and severity of the EM violations. It supports TSMC 65nm and 45nm EM rules for power and signal EM validation.

Dynamic Voltage Drop Analysis

RedHawk-MMX performs dynamic power analysis with consideration for package impact. It delivers ranking list of transistor pins with worst dynamic voltage drop, as well as color maps of dynamic voltage drop or current profile to assist designers in debugging dynamic power issues in their design.

Mixed-Mode SoC Analysis

RedHawk-MMX combines the transistor-level custom macro model and cell-based digital logic and allows the designers to view both the transistor-level and cell-based results in a single environment. RedHawk-MMX generates an accurate model based on SPICE-level device characterization and full macro modeling and validation, thus delivering a detailed view of the custom IP for SoC simulation.

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