Sentinel-CPM

Sentinel-CPM is a compact and SPICE-accurate model of the full-chip power delivery network. It contains spatial and temporal switching current profile, as well as parasitics of non-linear on-chip devices including decaps, loading capacitance, and power/ground coupling capacitance. Sentinel-CPM enables analysis, diagnostics, and optimization of system-level power integrity designs.

Sentinel-CPM enables IC-aware system verification including the following applications:

Dynamic voltage noise budgeting at board and package level
Global power delivery network (PDN) target impedance calculation and resonance prediction
Package and board optimization from prototyping to sign-off
System-in-Package (SiP) design analysis

Accuracy and Performance

Traditionally, the global power delivery network (PDN) is represented as a simplified model with a single current source, resistance, and capacitance network for the die, and lumped RLC parasitic elements for the package and the board.

This simplified model of the die’s power delivery network can result in inaccurate global power analysis as die current can influence the voltage drop through the system and the resistive and capacitive components of the die can determine the resonance frequency and its amplitude. Thus an accurate representation of the die’s PDN is critical in determining the quality of the system power integrity.

Sentinel-CPM generates power/ground network model as current sources and R, L, and C parasitics. Sentinel-CPM takes the entire network, which contains several linear and non-linear elements, and provides a reduced view of effective Rdie and Cdie for different frequencies of operation.

It also provides switching current information from the active logic that varies over time and space, reflecting the real operation of the chip over a range of frequencies. By including all the different parasitics and elements of the die, Sentinel-CPM offers a true representation of the chip.

One of the key motivations for generating a chip power model (CPM) is to perform IC-aware system design. Sentinel-CPM delivers reduced order model that enables designers to run multiple iterations of system design analysis and optimization. SPICE-based simulation of the package with CPM model will run within minutes versus full-chip dynamic power analysis that can take hours to perform.

Dynamic Voltage Noise Budgeting

The voltage drop distribution of the system is only as valid as the die model that is used for the system-level analysis. Using a simplified model of the die with triangular current profile can result in inaccurate view of the dynamic voltage drop distribution.

By using Sentinel-CPM in the package/board analysis, designers are able to gain more accurate view of the location and magnitude of the dynamic voltage drop, as it considers the real operation of the chip.

Impedance Calculation and Resonance Prediction

To design a good package, the designer needs to ensure that the input impedance is below the target impedance, and that the resonance frequency does not overlap with the functional frequency of the chip.

Sentinel-CPM contains Cdie (die capacitance) which impacts the frequency of the resonance, and Rdie (die resistance) which impacts the amplitude of the resonance. By generating different CPM for varying capacitive components, the designer can observe its impact on impedance profile and make the well informed decisions that meet the design criteria.

From Prototyping to Sign-off

Sentinel-CPM can be applied early in the design process to help direct the designers in package selection, pad placements, decap strategy, and impedance management. By having an accurate representation of the IC power deliver network (PDN), the designer can confidently make cost critical package/board design decisions to mitigate design failure risk and reduce overall system cost.

As design moves through the process, Sentinel-CPM can be used to incrementally improve the system design to avoid any last minute surprises at the end of the design cycle.

IC-aware Package and Board Analysis

Without an accurate model of the chip's power deliver network, engineers often times guard-band their package designs to protect against unknown power integrity issues. But this method can result in more complex package and/or more decaps on the board than necessary and ultimately higher cost system.

By using Sentinel-CPM, system designer gain access to accurate model of the IC PDN allowing them to analyze the impact of die-package LC resonance on the performance of global PDN and perform "IC-aware" voltage drop analysis in both time and frequency domain for package and PCB. Sentinel-CPM enables designers to perform better noise budgeting and optimize their package selection early in the design process to reduce cost and minimize design risk.

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